Merge branch 'master' of https://daniel12997@gitlab.com/AluminumTank/radec.git
This commit is contained in:
commit
496b61d77b
BIN
circuit/Circuit Sim (Text Version).zip
Normal file
BIN
circuit/Circuit Sim (Text Version).zip
Normal file
Binary file not shown.
6
circuit/RunCircuitSimulation.bat
Normal file
6
circuit/RunCircuitSimulation.bat
Normal file
@ -0,0 +1,6 @@
|
||||
@echo off
|
||||
set /p commandLine="Enter any command line arguments: "
|
||||
|
||||
"text circuit sim.exe" %commandLine%
|
||||
|
||||
pause
|
6
circuit/circuit0.txt
Normal file
6
circuit/circuit0.txt
Normal file
@ -0,0 +1,6 @@
|
||||
CIRCUIT SimpleCircuit
|
||||
INPUT A 1
|
||||
INPUT B 2
|
||||
OUTPUT C 3
|
||||
AND 2ns 1 2 3
|
||||
|
7
circuit/circuit0_v.txt
Normal file
7
circuit/circuit0_v.txt
Normal file
@ -0,0 +1,7 @@
|
||||
VECTOR SimpleCircuit
|
||||
INPUT A 0 0
|
||||
INPUT B 0 0
|
||||
INPUT A 4 1
|
||||
INPUT B 5 1
|
||||
|
||||
|
9
circuit/circuit1.txt
Normal file
9
circuit/circuit1.txt
Normal file
@ -0,0 +1,9 @@
|
||||
CIRCUIT Circuit1
|
||||
INPUT A 1
|
||||
INPUT B 3
|
||||
INPUT C 4
|
||||
OUTPUT D 5
|
||||
OUTPUT E 6
|
||||
NOT 2ns 1 2
|
||||
AND 3ns 2 3 5
|
||||
OR 3ns 4 5 6
|
7
circuit/circuit1_v.txt
Normal file
7
circuit/circuit1_v.txt
Normal file
@ -0,0 +1,7 @@
|
||||
VECTOR Circuit1
|
||||
INPUT A 0 0
|
||||
INPUT B 0 1
|
||||
INPUT C 0 0
|
||||
INPUT C 4 1
|
||||
INPUT A 6 1
|
||||
INPUT B 9 0
|
11
circuit/circuit2.txt
Normal file
11
circuit/circuit2.txt
Normal file
@ -0,0 +1,11 @@
|
||||
CIRCUIT Circuit2
|
||||
INPUT A 1
|
||||
INPUT B 3
|
||||
INPUT C 4
|
||||
INPUT D 5
|
||||
OUTPUT E 9
|
||||
NOT 2ns 1 2
|
||||
AND 5ns 2 3 6
|
||||
AND 5ns 4 5 7
|
||||
OR 4ns 6 7 8
|
||||
XOR 5ns 8 7 9
|
9
circuit/circuit2_v.txt
Normal file
9
circuit/circuit2_v.txt
Normal file
@ -0,0 +1,9 @@
|
||||
VECTOR Circuit2
|
||||
INPUT A 0 0
|
||||
INPUT B 0 1
|
||||
INPUT C 0 0
|
||||
INPUT D 0 1
|
||||
INPUT C 4 1
|
||||
INPUT A 6 1
|
||||
INPUT B 9 0
|
||||
INPUT D 12 X
|
9
circuit/circuit3.txt
Normal file
9
circuit/circuit3.txt
Normal file
@ -0,0 +1,9 @@
|
||||
CIRCUIT Circuit3
|
||||
INPUT A 1
|
||||
INPUT B 2
|
||||
INPUT C 3
|
||||
OUTPUT D 5
|
||||
OUTPUT E 6
|
||||
AND 2ns 1 2 4
|
||||
OR 3ns 4 3 5
|
||||
NOT 1ns 4 6
|
6
circuit/circuit3_v.txt
Normal file
6
circuit/circuit3_v.txt
Normal file
@ -0,0 +1,6 @@
|
||||
VECTOR Circuit3
|
||||
INPUT A 1 1
|
||||
INPUT B 1 0
|
||||
INPUT C 1 0
|
||||
INPUT B 7 1
|
||||
INPUT A 7 0
|
4
circuit/circuit4.txt
Normal file
4
circuit/circuit4.txt
Normal file
@ -0,0 +1,4 @@
|
||||
CIRCUIT JacubecCircuit
|
||||
INPUT A 1
|
||||
OUTPUT C 2
|
||||
NAND 2ns 1 2 2
|
3
circuit/circuit4_v.txt
Normal file
3
circuit/circuit4_v.txt
Normal file
@ -0,0 +1,3 @@
|
||||
VECTOR JacubecCircuit
|
||||
INPUT A 0 0
|
||||
INPUT A 1 1
|
8
circuit/circuit5.txt
Normal file
8
circuit/circuit5.txt
Normal file
@ -0,0 +1,8 @@
|
||||
CIRCUIT SimpleCircuit
|
||||
INPUT A 1
|
||||
INPUT B 2
|
||||
INPUT C 3
|
||||
OUTPUT OUT1 4
|
||||
OUTPUT OUT2 5
|
||||
AND 3ns 1 2 4
|
||||
OR 2ns 4 3 5
|
6
circuit/circuit5_v.txt
Normal file
6
circuit/circuit5_v.txt
Normal file
@ -0,0 +1,6 @@
|
||||
VECTOR SimpleCircuit
|
||||
INPUT A 0 1
|
||||
INPUT B 0 1
|
||||
INPUT C 0 0
|
||||
|
||||
|
8
circuit/circuit7.txt
Normal file
8
circuit/circuit7.txt
Normal file
@ -0,0 +1,8 @@
|
||||
CIRCUIT DrivesTwo
|
||||
INPUT A 1DrivesTwo
|
||||
OUTPUT B 3
|
||||
OUTPUT C 4
|
||||
NOT 2ns 1 3
|
||||
NOT 1ns 1 2
|
||||
NOT 1ns 2 4
|
||||
|
5
circuit/circuit7_v.txt
Normal file
5
circuit/circuit7_v.txt
Normal file
@ -0,0 +1,5 @@
|
||||
VECTOR DrivesTwo
|
||||
INPUT A 0 0
|
||||
INPUT A 3 1
|
||||
INPUT A 4 0
|
||||
|
7
circuit/circuit8.txt
Normal file
7
circuit/circuit8.txt
Normal file
@ -0,0 +1,7 @@
|
||||
CIRCUIT WhiteBoard
|
||||
INPUT A 1
|
||||
INPUT B 2
|
||||
OUTPUT C 3
|
||||
AND 2ns 1 2 4
|
||||
OR 3ns 2 4 3
|
||||
|
5
circuit/circuit8_v.txt
Normal file
5
circuit/circuit8_v.txt
Normal file
@ -0,0 +1,5 @@
|
||||
VECTOR WhiteBoard
|
||||
INPUT A 0 1
|
||||
INPUT B 0 0
|
||||
INPUT A 3 0
|
||||
|
7
circuit/ff.txt
Normal file
7
circuit/ff.txt
Normal file
@ -0,0 +1,7 @@
|
||||
CIRCUIT flipflop1
|
||||
INPUT R 1
|
||||
INPUT S 2
|
||||
OUTPUT O 3
|
||||
NOR 2ns 2 3 4
|
||||
NOR 2ns 1 4 3
|
||||
|
12
circuit/ff_v.txt
Normal file
12
circuit/ff_v.txt
Normal file
@ -0,0 +1,12 @@
|
||||
VECTOR flipflop1
|
||||
INPUT R 0 1
|
||||
INPUT S 0 1
|
||||
INPUT R 1 0
|
||||
INPUT S 1 0
|
||||
INPUT S 2 1
|
||||
INPUT S 3 0
|
||||
INPUT S 5 1
|
||||
INPUT S 6 0
|
||||
INPUT R 9 1
|
||||
INPUT R 10 0
|
||||
|
BIN
circuit/text circuit sim.exe
Normal file
BIN
circuit/text circuit sim.exe
Normal file
Binary file not shown.
@ -22,13 +22,9 @@ bool Simulation::parseCircuit(string fileName)
|
||||
in >> tmpString;
|
||||
in >> tmp1;
|
||||
|
||||
if (tmpType == "INPUT") {
|
||||
tmpWire = new Wire(tmp1, true, tmpString);
|
||||
wires.push_back(tmpWire);
|
||||
}
|
||||
else if (tmpType == "OUTPUT") {
|
||||
tmpWire = new Wire(tmp1, false, tmpString);
|
||||
wires.push_back(tmpWire);
|
||||
if (tmpType == "INPUT" || tmpType == "OUTPUT") {
|
||||
tmpWire = findWire(tmp1);
|
||||
tmpWire->convertToIO(tmpString);
|
||||
}
|
||||
else if (tmpType == "NOT") {
|
||||
in >> tmp2;
|
||||
@ -126,7 +122,11 @@ Wire * Simulation::findWire(int n)
|
||||
for (auto i = wires.begin(); i != wires.end(); ++i) {
|
||||
if (n == (**i).getNumber()) return *i;
|
||||
}
|
||||
return nullptr;
|
||||
|
||||
// if wire does not exist, create it, instantiating as an intermediary wire
|
||||
Wire * tmpWire = new Wire(n, false);
|
||||
wires.push_back(tmpWire);
|
||||
return tmpWire;
|
||||
}
|
||||
|
||||
int Simulation::getDelay(string d)
|
||||
|
@ -8,6 +8,7 @@ int main() {
|
||||
string fileName;
|
||||
Simulation e;
|
||||
|
||||
cout << "Please enter filename: ";
|
||||
getline(cin, fileName);
|
||||
e.parseCircuit(fileName);
|
||||
|
||||
@ -24,4 +25,4 @@ int main() {
|
||||
|
||||
// 4. Print the results of the simulation
|
||||
e.print();
|
||||
}
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user