implement circuit file parsing and add specs for rest of gates
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src/nandGate.cpp
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src/nandGate.cpp
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src/nandGate.h
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src/nandGate.h
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#ifndef AND
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#define AND
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class andGate : public gate {
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public:
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andGate(wire* wire1 = nullptr, wire* wire2 = nullptr, wire* wire3 = nullptr);
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int evaluate();
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};
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#endif // !AND
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src/norGate.cpp
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src/norGate.cpp
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src/norGate.h
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src/norGate.h
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#ifndef OR
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#define OR
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class orGate : public gate {
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orGate(wire* wire1 = nullptr, wire* wire2 = nullptr, wire* wire3 = nullptr);
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int evaluate();
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};
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#endif // !OR
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@ -2,7 +2,7 @@
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#define NOT
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class not : public gate {
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notGate(wire* wire1 = nullptr, wire* wire2 = nullptr);
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notGate(int delay, wire* wire1 = nullptr, wire* wire2 = nullptr);
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int evaluate();
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};
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@ -1,9 +1,15 @@
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#include <fstream>
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#include "wire.h"
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#include "pQueue.h"
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#include "orGate.h"
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#include "andGate.h"
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#include "notGate.h"
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using namespace std;
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int getDelay(string d);
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wire* findWire(int n, vector<wire*> wires);
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int main() {
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// 1. Parse circuit file to create in-memory data structure of Gates and Wires
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// to simulate
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@ -28,6 +34,80 @@ int main() {
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// 4. Print the results of the simulation
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}
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bool parseCircuit(gates, wires) {
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bool parseCircuit(gates, wires, fileName) {
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ifstream in;
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circuit.open(fileName + ".txt");
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if(in.fail()) {
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cerr << endl << fileName << ".txt could not be opened :(";
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exit(1);
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}
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string tmpString, tmpType;
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int tmp1, tmp2, tmp3;
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wire *tmpWire;
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gate *tmpGate;
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getline(in, tmpString);
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while(!in.eof()) {
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tmpType << in;
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tmpString << in;
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tmp1 << in;
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if(tmpType == "INPUT") {
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tmpWire = new wire(tmp1, true, tmpString);
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wires.push_back(tmpWire);
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}else if(tmpType == "OUTPUT") {
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tmpWire = new wire(tmp1, false, tmpString);
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wires.push_back(tmpWire);
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}else if(tmpType == "NOT") {
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tmp2 << in;
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tmpGate = new notGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2));
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gates.push_back(tmpGate);
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}else if(tmpType == "AND") {
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tmp2 << in;
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tmp3 << in;
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tmpGate = new andGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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}else if(tmpType == "NAND") {
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tmp2 << in;
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tmp3 << in;
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tmpGate = new nandGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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}else if(tmpType == "OR") {
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tmp2 << in;
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tmp3 << in;
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tmpGate = new orGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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}else if(tmpType == "XOR") {
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tmp2 << in;
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tmp3 << in;
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tmpGate = new xorGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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}else if(tmpType == "NOR") {
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tmp2 << in;
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tmp3 << in;
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tmpGate = new norGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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}else if(tmpType == "XNOR") {
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tmp2 << in;
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tmp3 << in;
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tmpGate = new xnorGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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}
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}
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}
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wire* findWire(int n, vector<wire*> wires) {
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//TODO
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}
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int getDelay(string d) {
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d.resize(d.size() - 2);
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return atoi(d.c_str());
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}
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@ -9,7 +9,7 @@ class gate;
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class wire {
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public:
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wire(int number, string name = "");
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wire(int number, bool io, string name = "");
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int getState() const;
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void setState(bool newValue, int setTime);
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src/xnorGate.cpp
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src/xnorGate.cpp
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src/xnorGate.h
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src/xnorGate.h
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#ifndef OR
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#define OR
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class orGate : public gate {
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orGate(wire* wire1 = nullptr, wire* wire2 = nullptr, wire* wire3 = nullptr);
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int evaluate();
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};
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#endif // !OR
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src/xorGate.cpp
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src/xorGate.cpp
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src/xorGate.h
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src/xorGate.h
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#ifndef OR
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#define OR
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class orGate : public gate {
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orGate(wire* wire1 = nullptr, wire* wire2 = nullptr, wire* wire3 = nullptr);
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int evaluate();
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};
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#endif // !OR
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