implement circuit file parsing and add specs for rest of gates

This commit is contained in:
Joel Beckmeyer 2017-04-09 21:42:07 -04:00
parent f8849ef25a
commit 54a5e91a12
11 changed files with 120 additions and 3 deletions

0
src/nandGate.cpp Normal file
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10
src/nandGate.h Normal file
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@ -0,0 +1,10 @@
#ifndef AND
#define AND
class andGate : public gate {
public:
andGate(wire* wire1 = nullptr, wire* wire2 = nullptr, wire* wire3 = nullptr);
int evaluate();
};
#endif // !AND

0
src/norGate.cpp Normal file
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9
src/norGate.h Normal file
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@ -0,0 +1,9 @@
#ifndef OR
#define OR
class orGate : public gate {
orGate(wire* wire1 = nullptr, wire* wire2 = nullptr, wire* wire3 = nullptr);
int evaluate();
};
#endif // !OR

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@ -2,7 +2,7 @@
#define NOT
class not : public gate {
notGate(wire* wire1 = nullptr, wire* wire2 = nullptr);
notGate(int delay, wire* wire1 = nullptr, wire* wire2 = nullptr);
int evaluate();
};

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@ -1,9 +1,15 @@
#include <fstream>
#include "wire.h"
#include "pQueue.h"
#include "orGate.h"
#include "andGate.h"
#include "notGate.h"
using namespace std;
int getDelay(string d);
wire* findWire(int n, vector<wire*> wires);
int main() {
// 1. Parse circuit file to create in-memory data structure of Gates and Wires
// to simulate
@ -28,6 +34,80 @@ int main() {
// 4. Print the results of the simulation
}
bool parseCircuit(gates, wires) {
bool parseCircuit(gates, wires, fileName) {
ifstream in;
circuit.open(fileName + ".txt");
if(in.fail()) {
cerr << endl << fileName << ".txt could not be opened :(";
exit(1);
}
string tmpString, tmpType;
int tmp1, tmp2, tmp3;
wire *tmpWire;
gate *tmpGate;
getline(in, tmpString);
while(!in.eof()) {
tmpType << in;
tmpString << in;
tmp1 << in;
if(tmpType == "INPUT") {
tmpWire = new wire(tmp1, true, tmpString);
wires.push_back(tmpWire);
}else if(tmpType == "OUTPUT") {
tmpWire = new wire(tmp1, false, tmpString);
wires.push_back(tmpWire);
}else if(tmpType == "NOT") {
tmp2 << in;
tmpGate = new notGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2));
gates.push_back(tmpGate);
}else if(tmpType == "AND") {
tmp2 << in;
tmp3 << in;
tmpGate = new andGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
findWire(tmp3));
gates.push_back(tmpGate);
}else if(tmpType == "NAND") {
tmp2 << in;
tmp3 << in;
tmpGate = new nandGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
findWire(tmp3));
gates.push_back(tmpGate);
}else if(tmpType == "OR") {
tmp2 << in;
tmp3 << in;
tmpGate = new orGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
findWire(tmp3));
gates.push_back(tmpGate);
}else if(tmpType == "XOR") {
tmp2 << in;
tmp3 << in;
tmpGate = new xorGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
findWire(tmp3));
gates.push_back(tmpGate);
}else if(tmpType == "NOR") {
tmp2 << in;
tmp3 << in;
tmpGate = new norGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
findWire(tmp3));
gates.push_back(tmpGate);
}else if(tmpType == "XNOR") {
tmp2 << in;
tmp3 << in;
tmpGate = new xnorGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
findWire(tmp3));
gates.push_back(tmpGate);
}
}
}
wire* findWire(int n, vector<wire*> wires) {
//TODO
}
int getDelay(string d) {
d.resize(d.size() - 2);
return atoi(d.c_str());
}

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@ -9,7 +9,7 @@ class gate;
class wire {
public:
wire(int number, string name = "");
wire(int number, bool io, string name = "");
int getState() const;
void setState(bool newValue, int setTime);

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src/xnorGate.cpp Normal file
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src/xnorGate.h Normal file
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@ -0,0 +1,9 @@
#ifndef OR
#define OR
class orGate : public gate {
orGate(wire* wire1 = nullptr, wire* wire2 = nullptr, wire* wire3 = nullptr);
int evaluate();
};
#endif // !OR

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src/xorGate.cpp Normal file
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9
src/xorGate.h Normal file
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@ -0,0 +1,9 @@
#ifndef OR
#define OR
class orGate : public gate {
orGate(wire* wire1 = nullptr, wire* wire2 = nullptr, wire* wire3 = nullptr);
int evaluate();
};
#endif // !OR