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stuff

This commit is contained in:
daniel 2017-04-24 22:14:00 -04:00
parent b326f08971
commit 681b4c91ad
20 changed files with 187 additions and 8 deletions
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18
Radec/Radec/Radec.vcxproj
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@ -175,6 +175,24 @@
<ItemGroup>
<None Include="..\..\readme.md" />
</ItemGroup>
<ItemGroup>
<Text Include="..\..\circuit\circuit0.txt" />
<Text Include="..\..\circuit\circuit0_v.txt" />
<Text Include="..\..\circuit\circuit1.txt" />
<Text Include="..\..\circuit\circuit1_v.txt" />
<Text Include="..\..\circuit\circuit2.txt" />
<Text Include="..\..\circuit\circuit2_v.txt" />
<Text Include="..\..\circuit\circuit3.txt" />
<Text Include="..\..\circuit\circuit3_v.txt" />
<Text Include="..\..\circuit\circuit4.txt" />
<Text Include="..\..\circuit\circuit4_v.txt" />
<Text Include="..\..\circuit\circuit5.txt" />
<Text Include="..\..\circuit\circuit5_v.txt" />
<Text Include="..\..\circuit\circuit7.txt" />
<Text Include="..\..\circuit\circuit7_v.txt" />
<Text Include="..\..\circuit\circuit8.txt" />
<Text Include="..\..\circuit\circuit8_v.txt" />
</ItemGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
</ImportGroup>

50
Radec/Radec/Radec.vcxproj.filters
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@ -98,4 +98,54 @@
<Filter>Resource Files</Filter>
</None>
</ItemGroup>
<ItemGroup>
<Text Include="..\..\circuit\circuit0.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit0_v.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit1.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit1_v.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit2.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit2_v.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit3.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit3_v.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit4.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit4_v.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit5.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit5_v.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit7.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit7_v.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit8.txt">
<Filter>Resource Files</Filter>
</Text>
<Text Include="..\..\circuit\circuit8_v.txt">
<Filter>Resource Files</Filter>
</Text>
</ItemGroup>
</Project>

5
Radec/Radec/circuit0.txt Normal file
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@ -0,0 +1,5 @@
CIRCUIT SimpleCircuit
INPUT A 1
INPUT B 2
OUTPUT C 3
AND 2ns 1 2 3

5
Radec/Radec/circuit0_v.txt Normal file
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@ -0,0 +1,5 @@
VECTOR SimpleCircuit
INPUT A 0 0
INPUT B 0 0
INPUT A 4 1
INPUT B 5 1

9
Radec/Radec/circuit1.txt Normal file
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@ -0,0 +1,9 @@
CIRCUIT Circuit1
INPUT A 1
INPUT B 3
INPUT C 4
OUTPUT D 5
OUTPUT E 6
NOT 2ns 1 2
AND 3ns 2 3 5
OR 3ns 4 5 6

7
Radec/Radec/circuit1_v.txt Normal file
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@ -0,0 +1,7 @@
VECTOR Circuit1
INPUT A 0 0
INPUT B 0 1
INPUT C 0 0
INPUT C 4 1
INPUT A 6 1
INPUT B 9 0

11
Radec/Radec/circuit2.txt Normal file
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@ -0,0 +1,11 @@
CIRCUIT Circuit2
INPUT A 1
INPUT B 3
INPUT C 4
INPUT D 5
OUTPUT E 9
NOT 2ns 1 2
AND 5ns 2 3 6
AND 5ns 4 5 7
OR 4ns 6 7 8
XOR 5ns 8 7 9

9
Radec/Radec/circuit2_v.txt Normal file
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@ -0,0 +1,9 @@
VECTOR Circuit2
INPUT A 0 0
INPUT B 0 1
INPUT C 0 0
INPUT D 0 1
INPUT C 4 1
INPUT A 6 1
INPUT B 9 0
INPUT D 12 X

9
Radec/Radec/circuit3.txt Normal file
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@ -0,0 +1,9 @@
CIRCUIT Circuit3
INPUT A 1
INPUT B 2
INPUT C 3
OUTPUT D 5
OUTPUT E 6
AND 2ns 1 2 4
OR 3ns 4 3 5
NOT 1ns 4 6

6
Radec/Radec/circuit3_v.txt Normal file
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@ -0,0 +1,6 @@
VECTOR Circuit3
INPUT A 1 1
INPUT B 1 0
INPUT C 1 0
INPUT B 7 1
INPUT A 7 0

4
Radec/Radec/circuit4.txt Normal file
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@ -0,0 +1,4 @@
CIRCUIT JacubecCircuit
INPUT A 1
OUTPUT C 2
NAND 2ns 1 2 2

3
Radec/Radec/circuit4_v.txt Normal file
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@ -0,0 +1,3 @@
VECTOR JacubecCircuit
INPUT A 0 0
INPUT A 1 1

8
Radec/Radec/circuit5.txt Normal file
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@ -0,0 +1,8 @@
CIRCUIT SimpleCircuit
INPUT A 1
INPUT B 2
INPUT C 3
OUTPUT OUT1 4
OUTPUT OUT2 5
AND 3ns 1 2 4
OR 2ns 4 3 5

6
Radec/Radec/circuit5_v.txt Normal file
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@ -0,0 +1,6 @@
VECTOR SimpleCircuit
INPUT A 0 1
INPUT B 0 1
INPUT C 0 0

8
Radec/Radec/circuit7.txt Normal file
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@ -0,0 +1,8 @@
CIRCUIT DrivesTwo
INPUT A 1DrivesTwo
OUTPUT B 3
OUTPUT C 4
NOT 2ns 1 3
NOT 1ns 1 2
NOT 1ns 2 4

5
Radec/Radec/circuit7_v.txt Normal file
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@ -0,0 +1,5 @@
VECTOR DrivesTwo
INPUT A 0 0
INPUT A 3 1
INPUT A 4 0

7
Radec/Radec/circuit8.txt Normal file
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@ -0,0 +1,7 @@
CIRCUIT WhiteBoard
INPUT A 1
INPUT B 2
OUTPUT C 3
AND 2ns 1 2 4
OR 3ns 2 4 3

5
Radec/Radec/circuit8_v.txt Normal file
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@ -0,0 +1,5 @@
VECTOR WhiteBoard
INPUT A 0 1
INPUT B 0 0
INPUT A 3 0

18
src/Simulation.cpp
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@ -90,7 +90,7 @@ bool Simulation::parseVector(string fileName) {
string tmpString;
int timeInt, valInt;
Wire *tmpWire;
Wire *tmpWire = nullptr;
// get rid of first line
getline(in, tmpString);
@ -127,10 +127,15 @@ void Simulation::simulate() {
if(doesChange) {
Gate * tmpGate;
int index = 0;
do{
while(true){
tmpGate = output->getGate(index++);
e.push(tmpGate->evaluate(tmpEvent.getTime()));
}while(tmpGate != nullptr);
if (tmpGate != nullptr) {
e.push(tmpGate->evaluate(tmpEvent.getTime()));
}
else {
break;
}
}
}
}
}
@ -149,14 +154,13 @@ void Simulation::print()
// now iterate through wires, printing each of them
for(auto i = wires.begin(); i != wires.end(); ++i) {
(**i).setLast(lastTime);
cout << *i;
cout << **i;
}
int t = 0;
cout << setw(10) << "TIME";
cout << setw(5);
while(t <= 60 && t <= lastTime) {
cout << t;
cout << setw(5) << t;
t += 5;
}
}

2
src/Wire.cpp
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@ -57,7 +57,7 @@ void Wire::convertToIO(string newName)
Gate * Wire::getGate(int index)
{
if (index >= gates.size()) {
if (index < gates.size()) {
return gates[index];
}
return nullptr;