stuff
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parent
b326f08971
commit
681b4c91ad
@ -175,6 +175,24 @@
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<ItemGroup>
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<None Include="..\..\readme.md" />
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</ItemGroup>
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<ItemGroup>
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<Text Include="..\..\circuit\circuit0.txt" />
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<Text Include="..\..\circuit\circuit0_v.txt" />
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<Text Include="..\..\circuit\circuit1.txt" />
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<Text Include="..\..\circuit\circuit1_v.txt" />
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<Text Include="..\..\circuit\circuit2.txt" />
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<Text Include="..\..\circuit\circuit2_v.txt" />
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<Text Include="..\..\circuit\circuit3.txt" />
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<Text Include="..\..\circuit\circuit3_v.txt" />
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<Text Include="..\..\circuit\circuit4.txt" />
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<Text Include="..\..\circuit\circuit4_v.txt" />
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<Text Include="..\..\circuit\circuit5.txt" />
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<Text Include="..\..\circuit\circuit5_v.txt" />
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<Text Include="..\..\circuit\circuit7.txt" />
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<Text Include="..\..\circuit\circuit7_v.txt" />
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<Text Include="..\..\circuit\circuit8.txt" />
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<Text Include="..\..\circuit\circuit8_v.txt" />
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</ItemGroup>
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<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
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<ImportGroup Label="ExtensionTargets">
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</ImportGroup>
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@ -98,4 +98,54 @@
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<Filter>Resource Files</Filter>
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</None>
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</ItemGroup>
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<ItemGroup>
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<Text Include="..\..\circuit\circuit0.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit0_v.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit1.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit1_v.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit2.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit2_v.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit3.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit3_v.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit4.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit4_v.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit5.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit5_v.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit7.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit7_v.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit8.txt">
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<Filter>Resource Files</Filter>
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</Text>
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<Text Include="..\..\circuit\circuit8_v.txt">
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<Filter>Resource Files</Filter>
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</Text>
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</ItemGroup>
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</Project>
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5
Radec/Radec/circuit0.txt
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5
Radec/Radec/circuit0.txt
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CIRCUIT SimpleCircuit
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INPUT A 1
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INPUT B 2
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OUTPUT C 3
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AND 2ns 1 2 3
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5
Radec/Radec/circuit0_v.txt
Normal file
5
Radec/Radec/circuit0_v.txt
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@ -0,0 +1,5 @@
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VECTOR SimpleCircuit
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INPUT A 0 0
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INPUT B 0 0
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INPUT A 4 1
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INPUT B 5 1
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9
Radec/Radec/circuit1.txt
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9
Radec/Radec/circuit1.txt
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CIRCUIT Circuit1
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INPUT A 1
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INPUT B 3
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INPUT C 4
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OUTPUT D 5
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OUTPUT E 6
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NOT 2ns 1 2
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AND 3ns 2 3 5
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OR 3ns 4 5 6
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7
Radec/Radec/circuit1_v.txt
Normal file
7
Radec/Radec/circuit1_v.txt
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VECTOR Circuit1
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INPUT A 0 0
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INPUT B 0 1
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INPUT C 0 0
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INPUT C 4 1
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INPUT A 6 1
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INPUT B 9 0
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11
Radec/Radec/circuit2.txt
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11
Radec/Radec/circuit2.txt
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CIRCUIT Circuit2
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INPUT A 1
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INPUT B 3
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INPUT C 4
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INPUT D 5
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OUTPUT E 9
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NOT 2ns 1 2
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AND 5ns 2 3 6
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AND 5ns 4 5 7
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OR 4ns 6 7 8
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XOR 5ns 8 7 9
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9
Radec/Radec/circuit2_v.txt
Normal file
9
Radec/Radec/circuit2_v.txt
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VECTOR Circuit2
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INPUT A 0 0
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INPUT B 0 1
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INPUT C 0 0
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INPUT D 0 1
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INPUT C 4 1
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INPUT A 6 1
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INPUT B 9 0
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INPUT D 12 X
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9
Radec/Radec/circuit3.txt
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9
Radec/Radec/circuit3.txt
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CIRCUIT Circuit3
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INPUT A 1
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INPUT B 2
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INPUT C 3
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OUTPUT D 5
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OUTPUT E 6
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AND 2ns 1 2 4
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OR 3ns 4 3 5
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NOT 1ns 4 6
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6
Radec/Radec/circuit3_v.txt
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6
Radec/Radec/circuit3_v.txt
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VECTOR Circuit3
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INPUT A 1 1
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INPUT B 1 0
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INPUT C 1 0
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INPUT B 7 1
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INPUT A 7 0
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4
Radec/Radec/circuit4.txt
Normal file
4
Radec/Radec/circuit4.txt
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CIRCUIT JacubecCircuit
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INPUT A 1
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OUTPUT C 2
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NAND 2ns 1 2 2
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3
Radec/Radec/circuit4_v.txt
Normal file
3
Radec/Radec/circuit4_v.txt
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VECTOR JacubecCircuit
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INPUT A 0 0
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INPUT A 1 1
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8
Radec/Radec/circuit5.txt
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8
Radec/Radec/circuit5.txt
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CIRCUIT SimpleCircuit
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INPUT A 1
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INPUT B 2
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INPUT C 3
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OUTPUT OUT1 4
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OUTPUT OUT2 5
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AND 3ns 1 2 4
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OR 2ns 4 3 5
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6
Radec/Radec/circuit5_v.txt
Normal file
6
Radec/Radec/circuit5_v.txt
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VECTOR SimpleCircuit
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INPUT A 0 1
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INPUT B 0 1
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INPUT C 0 0
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8
Radec/Radec/circuit7.txt
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8
Radec/Radec/circuit7.txt
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CIRCUIT DrivesTwo
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INPUT A 1DrivesTwo
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OUTPUT B 3
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OUTPUT C 4
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NOT 2ns 1 3
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NOT 1ns 1 2
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NOT 1ns 2 4
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5
Radec/Radec/circuit7_v.txt
Normal file
5
Radec/Radec/circuit7_v.txt
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VECTOR DrivesTwo
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INPUT A 0 0
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INPUT A 3 1
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INPUT A 4 0
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7
Radec/Radec/circuit8.txt
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7
Radec/Radec/circuit8.txt
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CIRCUIT WhiteBoard
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INPUT A 1
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INPUT B 2
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OUTPUT C 3
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AND 2ns 1 2 4
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OR 3ns 2 4 3
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5
Radec/Radec/circuit8_v.txt
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5
Radec/Radec/circuit8_v.txt
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VECTOR WhiteBoard
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INPUT A 0 1
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INPUT B 0 0
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INPUT A 3 0
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@ -90,7 +90,7 @@ bool Simulation::parseVector(string fileName) {
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string tmpString;
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int timeInt, valInt;
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Wire *tmpWire;
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Wire *tmpWire = nullptr;
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// get rid of first line
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getline(in, tmpString);
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@ -127,10 +127,15 @@ void Simulation::simulate() {
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if(doesChange) {
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Gate * tmpGate;
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int index = 0;
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do{
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while(true){
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tmpGate = output->getGate(index++);
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e.push(tmpGate->evaluate(tmpEvent.getTime()));
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}while(tmpGate != nullptr);
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if (tmpGate != nullptr) {
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e.push(tmpGate->evaluate(tmpEvent.getTime()));
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}
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else {
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break;
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}
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}
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}
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}
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}
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@ -149,14 +154,13 @@ void Simulation::print()
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// now iterate through wires, printing each of them
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for(auto i = wires.begin(); i != wires.end(); ++i) {
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(**i).setLast(lastTime);
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cout << *i;
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cout << **i;
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}
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int t = 0;
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cout << setw(10) << "TIME";
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cout << setw(5);
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while(t <= 60 && t <= lastTime) {
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cout << t;
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cout << setw(5) << t;
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t += 5;
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}
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}
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Gate * Wire::getGate(int index)
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{
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if (index >= gates.size()) {
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if (index < gates.size()) {
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return gates[index];
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}
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return nullptr;
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