Add the simulation class and start populating it.

Radec/Radec/Radec.vcxproj

@@ -153,7 +153,7 @@
     <ClInclude Include="..\..\src\norGate.h" />
     <ClInclude Include="..\..\src\notGate.h" />
     <ClInclude Include="..\..\src\orGate.h" />
-    <ClInclude Include="..\..\src\pQueue.h" />
+    <ClInclude Include="..\..\src\Simulation.h" />
     <ClInclude Include="..\..\src\wire.h" />
     <ClInclude Include="..\..\src\xnorGate.h" />
     <ClInclude Include="..\..\src\xorGate.h" />
@@ -166,7 +166,8 @@
     <ClCompile Include="..\..\src\norGate.cpp" />
     <ClCompile Include="..\..\src\notGate.cpp" />
     <ClCompile Include="..\..\src\orGate.cpp" />
-    <ClCompile Include="..\..\src\pQueue.cpp" />
+    <ClCompile Include="..\..\src\radec.cpp" />
+    <ClCompile Include="..\..\src\Simulation.cpp" />
     <ClCompile Include="..\..\src\wire.cpp" />
     <ClCompile Include="..\..\src\xnorGate.cpp" />
     <ClCompile Include="..\..\src\xorGate.cpp" />

Radec/Radec/Radec.vcxproj.filters

@@ -30,9 +30,6 @@
     <ClInclude Include="..\..\src\event.h">
       <Filter>Header Files</Filter>
     </ClInclude>
-    <ClInclude Include="..\..\src\pQueue.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
     <ClInclude Include="..\..\src\andGate.h">
       <Filter>Header Files\Gates</Filter>
     </ClInclude>
@@ -54,6 +51,9 @@
     <ClInclude Include="..\..\src\xorGate.h">
       <Filter>Header Files\Gates</Filter>
     </ClInclude>
+    <ClInclude Include="..\..\src\Simulation.h">
+      <Filter>Header Files</Filter>
+    </ClInclude>
   </ItemGroup>
   <ItemGroup>
     <ClCompile Include="..\..\src\wire.cpp">
@@ -62,9 +62,6 @@
     <ClCompile Include="..\..\src\event.cpp">
       <Filter>Source Files</Filter>
     </ClCompile>
-    <ClCompile Include="..\..\src\pQueue.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
     <ClCompile Include="..\..\src\andGate.cpp">
       <Filter>Source Files\Gates</Filter>
     </ClCompile>
@@ -89,5 +86,11 @@
     <ClCompile Include="..\..\src\xorGate.cpp">
       <Filter>Source Files\Gates</Filter>
     </ClCompile>
+    <ClCompile Include="..\..\src\Simulation.cpp">
+      <Filter>Source Files</Filter>
+    </ClCompile>
+    <ClCompile Include="..\..\src\radec.cpp">
+      <Filter>Source Files</Filter>
+    </ClCompile>
   </ItemGroup>
 </Project>

src/Simulation.cpp

@@ -0,0 +1,88 @@
+#include "Simulation.h"
+
+bool Simulation::parse(string fileName)
+{
+	ifstream in;
+	circuit.open(fileName + ".txt");
+	if (in.fail()) {
+		cerr << endl << fileName << ".txt could not be opened :(";
+		exit(1);
+	}
+
+	string tmpString, tmpType;
+	int tmp1, tmp2, tmp3;
+	wire *tmpWire;
+	gate *tmpGate;
+	getline(in, tmpString);
+
+	while (!in.eof()) {
+		tmpType << in;
+
+		tmpString << in;
+		tmp1 << in;
+		if (tmpType == "INPUT") {
+			tmpWire = new wire(tmp1, true, tmpString);
+			wires.push_back(tmpWire);
+		}
+		else if (tmpType == "OUTPUT") {
+			tmpWire = new wire(tmp1, false, tmpString);
+			wires.push_back(tmpWire);
+		}
+		else if (tmpType == "NOT") {
+			tmp2 << in;
+			tmpGate = new notGate(getDelay(tmpString), findWire(tmp1),
+				findWire(tmp2));
+			gates.push_back(tmpGate);
+		}
+		else if (tmpType == "AND") {
+			tmp2 << in;
+			tmp3 << in;
+			tmpGate = new andGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
+				findWire(tmp3));
+			gates.push_back(tmpGate);
+		}
+		else if (tmpType == "NAND") {
+			tmp2 << in;
+			tmp3 << in;
+			tmpGate = new nandGate(getDelay(tmpString), findWire(tmp1),
+				findWire(tmp2), findWire(tmp3));
+			gates.push_back(tmpGate);
+		}
+		else if (tmpType == "OR") {
+			tmp2 << in;
+			tmp3 << in;
+			tmpGate = new orGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
+				findWire(tmp3));
+			gates.push_back(tmpGate);
+		}
+		else if (tmpType == "XOR") {
+			tmp2 << in;
+			tmp3 << in;
+			tmpGate = new xorGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
+				findWire(tmp3));
+			gates.push_back(tmpGate);
+		}
+		else if (tmpType == "NOR") {
+			tmp2 << in;
+			tmp3 << in;
+			tmpGate = new norGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
+				findWire(tmp3));
+			gates.push_back(tmpGate);
+		}
+		else if (tmpType == "XNOR") {
+			tmp2 << in;
+			tmp3 << in;
+			tmpGate = new xnorGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
+				findWire(tmp3));
+			gates.push_back(tmpGate);
+		}
+	}
+}
+
+void Simulation::simulate()
+{
+}
+
+void Simulation::print()
+{
+}

src/Simulation.h

@@ -0,0 +1,32 @@
+#ifndef SIMULATION
+#define SIMULATION
+
+#include "wire.h"
+#include "event.h"
+#include "gate.h"
+#include "andGate.h"
+#include "nandGate.h"
+#include "orGate.h"
+#include "norGate.h"
+#include "xnorGate.h"
+#include "xorGate.h"
+#include "notGate.h"
+#include <string>
+#include <vector>
+#include <fstream>
+#include <iostream>
+
+using namespace std;
+
+class Simulation {
+	public:
+		bool parse(string fileName);
+		void simulate();
+		void print();
+	private:
+		priority_queue<event> e;
+		vector<gate*> gates;
+		vector<wire*> wires;
+};
+
+#endif // !SIMULATION

src/gate.h

@@ -11,7 +11,7 @@ class gate {
 		wire *in1, *in2, *out;
 		priority_queue<event> *e;
 		int delay;
-		priority_queue<event> *e;
+		
 };
 
 #endif // !GATE