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A simple, terminal-based boolean logic simulator
44 Commits 1 Branch 0 Tags 429 KiB
C++ 99.4%
Batchfile 0.6%
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daniel a5e16c9347 Add the simulation class and start populating it.
2017-04-20 12:41:43 -04:00
Radec Add the simulation class and start populating it. 2017-04-20 12:41:43 -04:00
src Add the simulation class and start populating it. 2017-04-20 12:41:43 -04:00
.gitattributes Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
.gitignore Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
readme.md implement event class 2017-04-10 17:15:05 -04:00

readme.md

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely