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radec
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13d85a46513fbe7f98018b6adf159d30f0b946cd
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daniel
13d85a4651
Add the getter of delay in the gate classes. Add the findeWire and get delay functions for the simulation class. Fix the order of the input to: "in >> data" from "data << in".
2017-04-20 13:01:04 -04:00
Radec
Add the simulation class and start populating it.
2017-04-20 12:41:43 -04:00
src
Add the getter of delay in the gate classes. Add the findeWire and get delay functions for the simulation class. Fix the order of the input to: "in >> data" from "data << in".
2017-04-20 13:01:04 -04:00
.gitattributes
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
.gitignore
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
readme.md
implement event class
2017-04-10 17:15:05 -04:00
readme.md
RADEC
TODO
implement vector file parsing
define all classes more completely
Description
A simple, terminal-based boolean logic simulator
logic
logic-circuit
logic-gates
terminal-based
Readme
429
KiB
Languages
C++
99.4%
Batchfile
0.6%
