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A simple, terminal-based boolean logic simulator
62 Commits 1 Branch 0 Tags 429 KiB
C++ 99.4%
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daniel 17dc12732c Make wire history better
2017-04-23 20:30:15 -04:00
Radec Fix the gate evaluate definition to return event 2017-04-23 19:29:29 -04:00
src Make wire history better 2017-04-23 20:30:15 -04:00
.gitattributes Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
.gitignore Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
readme.md Added something to the TODO. 2017-04-20 13:02:48 -04:00

readme.md

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely
  • Add constructors for the gate classes which are used in the simulation class to make them.