TnSb/radec
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
27 Commits 1 Branch 0 Tags
517d6e333e1e24b20c2d5a43d0ee1abd24ca97ac
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Joel Beckmeyer 517d6e333e fix boolean name to be more accurate
2017-04-10 21:02:41 -04:00
Radec
Define the wire class
2017-04-10 18:57:03 -04:00
src
fix boolean name to be more accurate
2017-04-10 21:02:41 -04:00
.gitattributes
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
.gitignore
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
readme.md
implement event class
2017-04-10 17:15:05 -04:00

readme.md

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely
Description
A simple, terminal-based boolean logic simulator
logiclogic-circuitlogic-gatesterminal-based
Readme 429 KiB
Languages
C++ 99.4%
Batchfile 0.6%