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Joel Beckmeyer 53198547c0 add simple evaluation to andGate
2017-04-10 19:49:35 -04:00
Radec
Define the wire class
2017-04-10 18:57:03 -04:00
src
add simple evaluation to andGate
2017-04-10 19:49:35 -04:00
.gitattributes
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
.gitignore
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
readme.md
implement event class
2017-04-10 17:15:05 -04:00

readme.md

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely
Description
A simple, terminal-based boolean logic simulator
logiclogic-circuitlogic-gatesterminal-based
Readme 429 KiB
Languages
C++ 99.4%
Batchfile 0.6%