TnSb/radec
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
54 Commits 1 Branch 0 Tags
5d61e058b47d3e7034d3ec2160ce3368268ef866
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE

readme.md

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely
  • Add constructors for the gate classes which are used in the simulation class to make them.
Description
A simple, terminal-based boolean logic simulator
logiclogic-circuitlogic-gatesterminal-based
Readme 429 KiB
Languages
C++ 99.4%
Batchfile 0.6%