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Joel Beckmeyer 66e5ae9418 finish fixing class names
2017-04-23 19:18:11 -04:00
Radec
Added something to the TODO.
2017-04-20 13:02:48 -04:00
src
finish fixing class names
2017-04-23 19:18:11 -04:00
.gitattributes
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
.gitignore
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
readme.md
Added something to the TODO.
2017-04-20 13:02:48 -04:00

readme.md

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely
  • Add constructors for the gate classes which are used in the simulation class to make them.
Description
A simple, terminal-based boolean logic simulator
logiclogic-circuitlogic-gatesterminal-based
Readme 429 KiB
Languages
C++ 99.4%
Batchfile 0.6%