This website requires JavaScript.
Explore
Help
Sign In
TnSb
/
radec
Watch
1
Star
0
Fork
0
You've already forked radec
Code
Issues
Pull Requests
Projects
Releases
Wiki
Activity
88
Commits
1
Branch
0
Tags
75f7f3abd99602421c18febdb1ec6f9e6175542e
Go to file
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
Joel Beckmeyer
75f7f3abd9
Merge branch 'master' of
https://gitlab.com/AluminumTank/radec
2017-04-24 21:09:55 -04:00
circuit
add the amazing test cases
2017-04-23 20:57:44 -04:00
Radec
Fix the gate evaluate definition to return event
2017-04-23 19:29:29 -04:00
src
Merge branch 'master' of
https://gitlab.com/AluminumTank/radec
2017-04-24 21:09:55 -04:00
.gitattributes
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
.gitignore
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
readme.md
actually update readme
2017-04-23 20:32:31 -04:00
readme.md
RADEC
TODO
implement printing
debug: circuit parsing
debug: vector parsing
debug: simulation
debug: printing
Description
A simple, terminal-based boolean logic simulator
logic
logic-circuit
logic-gates
terminal-based
Readme
429
KiB
Languages
C++
99.4%
Batchfile
0.6%
