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A simple, terminal-based boolean logic simulator
48 Commits 1 Branch 0 Tags 429 KiB
C++ 99.4%
Batchfile 0.6%
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daniel 8cf81bed17 Added something to the TODO.
2017-04-20 13:02:48 -04:00
Radec Added something to the TODO. 2017-04-20 13:02:48 -04:00
src Add the getter of delay in the gate classes. Add the findeWire and get delay functions for the simulation class. Fix the order of the input to: "in >> data" from "data << in". 2017-04-20 13:01:04 -04:00
.gitattributes Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
.gitignore Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
readme.md Added something to the TODO. 2017-04-20 13:02:48 -04:00

readme.md

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely
  • Add constructors for the gate classes which are used in the simulation class to make them.