A simple, terminal-based boolean logic simulator
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Radec Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
src add some functionality to andGate class 2017-04-10 19:38:54 -04:00
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readme.md implement event class 2017-04-10 17:15:05 -04:00

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely