TnSb/radec

A simple, terminal-based boolean logic simulator

logic logic-circuit logic-gates terminal-based

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daniel a005f92560 Merge branch 'master' of https://daniel12997@gitlab.com/AluminumTank/radec.git		2017-04-24 21:06:00 -04:00
circuit	add the amazing test cases	2017-04-23 20:57:44 -04:00
Radec	Fix the gate evaluate definition to return event	2017-04-23 19:29:29 -04:00
src	Merge branch 'master' of https://daniel12997@gitlab.com/AluminumTank/radec.git	2017-04-24 21:06:00 -04:00
.gitattributes	Add the basic class defineition for Wire and Gate.	2017-04-04 13:37:46 -04:00
.gitignore	Add the basic class defineition for Wire and Gate.	2017-04-04 13:37:46 -04:00
readme.md	actually update readme	2017-04-23 20:32:31 -04:00

readme.md

RADEC

TODO

implement printing
debug: circuit parsing
debug: vector parsing
debug: simulation
debug: printing