TnSb/radec
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
A simple, terminal-based boolean logic simulator
55 Commits 1 Branch 0 Tags 429 KiB
C++ 99.4%
Batchfile 0.6%
c808dd3ec2
Go to file
Joel Beckmeyer c808dd3ec2 Merge branch 'master' of https://gitlab.com/AluminumTank/radec
2017-04-23 19:28:01 -04:00
Radec Added something to the TODO. 2017-04-20 13:02:48 -04:00
src Merge branch 'master' of https://gitlab.com/AluminumTank/radec 2017-04-23 19:28:01 -04:00
.gitattributes Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
.gitignore Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
readme.md Added something to the TODO. 2017-04-20 13:02:48 -04:00

readme.md

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely
  • Add constructors for the gate classes which are used in the simulation class to make them.