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A simple, terminal-based boolean logic simulator
113 Commits 1 Branch 0 Tags 429 KiB
C++ 99.4%
Batchfile 0.6%
ed164155f8
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daniel ed164155f8 made formating better
2017-04-25 20:51:41 -04:00
circuit finish the program and fix when a wire goes undefined 2017-04-25 14:38:15 -04:00
Radec finish the program and fix when a wire goes undefined 2017-04-25 14:38:15 -04:00
src made formating better 2017-04-25 20:51:41 -04:00
.gitattributes Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
.gitignore Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
readme.md update readme 2017-04-24 22:41:01 -04:00

readme.md

RADEC

TODO

  • debug: circuit parsing
  • debug: vector parsing
  • debug: simulation
  • debug: printing