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Joel Beckmeyer f8849ef25a cleanup repo
2017-04-06 13:38:51 -04:00
Radec
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
src
cleanup repo
2017-04-06 13:38:51 -04:00
.gitattributes
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
.gitignore
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
readme.md
update readme
2017-04-06 13:36:32 -04:00

readme.md

RADEC

TODO

  • implement circuit/vector file parsing
  • develop pQueue class
  • declare rest of needed gate types
  • define all classes more completely
Description
A simple, terminal-based boolean logic simulator
logiclogic-circuitlogic-gatesterminal-based
Readme 429 KiB
Languages
C++ 99.4%
Batchfile 0.6%