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fb3713e44f3bf7191c5524fcae3e81ea83fd5ee9
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daniel fb3713e44f Return 0
2017-04-26 19:30:24 -04:00
circuit
finish the program and fix when a wire goes undefined
2017-04-25 14:38:15 -04:00
Radec
finish the program and fix when a wire goes undefined
2017-04-25 14:38:15 -04:00
src
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2017-04-26 19:30:24 -04:00
.gitattributes
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
.gitignore
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
readme.md
update readme
2017-04-24 22:41:01 -04:00

readme.md

RADEC

TODO

  • debug: circuit parsing
  • debug: vector parsing
  • debug: simulation
  • debug: printing
Description
A simple, terminal-based boolean logic simulator
logiclogic-circuitlogic-gatesterminal-based
Readme 429 KiB
Languages
C++ 99.4%
Batchfile 0.6%