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radec
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Merge branch 'master' of https://daniel12997@gitlab.com/AluminumTank/radec.git

This commit is contained in:
daniel 2017-04-24 23:06:27 -04:00
parent c15879016b 93612d7e1d
commit 21084a033e
2 changed files with 9 additions and 10 deletions
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1
readme.md
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@ -1,7 +1,6 @@
# RADEC # RADEC
# TODO # TODO
* implement printing
* debug: circuit parsing * debug: circuit parsing
* debug: vector parsing * debug: vector parsing
* debug: simulation * debug: simulation

18
src/Simulation.cpp
View File

@ -19,10 +19,10 @@ bool Simulation::parseCircuit(string fileName)
// get rid of first line // get rid of first line
getline(in, tmpString); getline(in, tmpString);
while (!in.eof()) { while (true) {
in >> tmpType; if (!(in >> tmpType)) break;
in >> tmpString; if (!(in >> tmpString)) break;
in >> tmp1; if (!(in >> tmp1)) break;
if (tmpType == "INPUT" || tmpType == "OUTPUT") { if (tmpType == "INPUT" || tmpType == "OUTPUT") {
tmpWire = findWire(tmp1); tmpWire = findWire(tmp1);
@ -117,11 +117,11 @@ bool Simulation::parseVector(string fileName) {
// get rid of first line // get rid of first line
getline(in, tmpString); getline(in, tmpString);
while(!in.eof()) { while(true) {
in >> tmpString; if (!(in >> tmpString)) break;
in >> tmpString; if (!(in >> tmpString)) break;
in >> timeInt; if (!(in >> tmpInt)) break;
in >> valInt; if (!(in >> valInt)) break;
for(auto i = wires.begin(); i != wires.end(); ++i) { for(auto i = wires.begin(); i != wires.end(); ++i) {
if((**i).getName() == tmpString) { if((**i).getName() == tmpString) {