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A simple, terminal-based boolean logic simulator
102 Commits 1 Branch 0 Tags 429 KiB
C++ 99.4%
Batchfile 0.6%
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daniel 21084a033e Merge branch 'master' of https://daniel12997@gitlab.com/AluminumTank/radec.git
2017-04-24 23:06:27 -04:00
circuit add the amazing test cases 2017-04-23 20:57:44 -04:00
Radec stuff 2017-04-24 22:14:00 -04:00
src Merge branch 'master' of https://daniel12997@gitlab.com/AluminumTank/radec.git 2017-04-24 23:06:27 -04:00
.gitattributes Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
.gitignore Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
readme.md update readme 2017-04-24 22:41:01 -04:00

readme.md

RADEC

TODO

  • debug: circuit parsing
  • debug: vector parsing
  • debug: simulation
  • debug: printing