Merge branch 'master' of https://daniel12997@gitlab.com/AluminumTank/radec.git
This commit is contained in:
commit
496b61d77b
BIN
circuit/Circuit Sim (Text Version).zip
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BIN
circuit/Circuit Sim (Text Version).zip
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6
circuit/RunCircuitSimulation.bat
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6
circuit/RunCircuitSimulation.bat
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@echo off
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set /p commandLine="Enter any command line arguments: "
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"text circuit sim.exe" %commandLine%
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pause
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6
circuit/circuit0.txt
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6
circuit/circuit0.txt
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CIRCUIT SimpleCircuit
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INPUT A 1
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INPUT B 2
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OUTPUT C 3
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AND 2ns 1 2 3
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7
circuit/circuit0_v.txt
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7
circuit/circuit0_v.txt
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VECTOR SimpleCircuit
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INPUT A 0 0
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INPUT B 0 0
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INPUT A 4 1
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INPUT B 5 1
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9
circuit/circuit1.txt
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9
circuit/circuit1.txt
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CIRCUIT Circuit1
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INPUT A 1
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INPUT B 3
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INPUT C 4
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OUTPUT D 5
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OUTPUT E 6
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NOT 2ns 1 2
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AND 3ns 2 3 5
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OR 3ns 4 5 6
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7
circuit/circuit1_v.txt
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7
circuit/circuit1_v.txt
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@ -0,0 +1,7 @@
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VECTOR Circuit1
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INPUT A 0 0
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INPUT B 0 1
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INPUT C 0 0
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INPUT C 4 1
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INPUT A 6 1
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INPUT B 9 0
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11
circuit/circuit2.txt
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11
circuit/circuit2.txt
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@ -0,0 +1,11 @@
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CIRCUIT Circuit2
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INPUT A 1
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INPUT B 3
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INPUT C 4
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INPUT D 5
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OUTPUT E 9
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NOT 2ns 1 2
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AND 5ns 2 3 6
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AND 5ns 4 5 7
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OR 4ns 6 7 8
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XOR 5ns 8 7 9
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9
circuit/circuit2_v.txt
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9
circuit/circuit2_v.txt
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VECTOR Circuit2
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INPUT A 0 0
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INPUT B 0 1
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INPUT C 0 0
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INPUT D 0 1
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INPUT C 4 1
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INPUT A 6 1
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INPUT B 9 0
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INPUT D 12 X
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9
circuit/circuit3.txt
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9
circuit/circuit3.txt
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CIRCUIT Circuit3
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INPUT A 1
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INPUT B 2
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INPUT C 3
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OUTPUT D 5
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OUTPUT E 6
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AND 2ns 1 2 4
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OR 3ns 4 3 5
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NOT 1ns 4 6
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6
circuit/circuit3_v.txt
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6
circuit/circuit3_v.txt
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VECTOR Circuit3
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INPUT A 1 1
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INPUT B 1 0
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INPUT C 1 0
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INPUT B 7 1
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INPUT A 7 0
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4
circuit/circuit4.txt
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4
circuit/circuit4.txt
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CIRCUIT JacubecCircuit
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INPUT A 1
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OUTPUT C 2
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NAND 2ns 1 2 2
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3
circuit/circuit4_v.txt
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3
circuit/circuit4_v.txt
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VECTOR JacubecCircuit
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INPUT A 0 0
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INPUT A 1 1
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8
circuit/circuit5.txt
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8
circuit/circuit5.txt
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CIRCUIT SimpleCircuit
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INPUT A 1
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INPUT B 2
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INPUT C 3
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OUTPUT OUT1 4
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OUTPUT OUT2 5
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AND 3ns 1 2 4
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OR 2ns 4 3 5
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6
circuit/circuit5_v.txt
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6
circuit/circuit5_v.txt
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VECTOR SimpleCircuit
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INPUT A 0 1
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INPUT B 0 1
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INPUT C 0 0
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8
circuit/circuit7.txt
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8
circuit/circuit7.txt
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CIRCUIT DrivesTwo
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INPUT A 1DrivesTwo
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OUTPUT B 3
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OUTPUT C 4
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NOT 2ns 1 3
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NOT 1ns 1 2
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NOT 1ns 2 4
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5
circuit/circuit7_v.txt
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5
circuit/circuit7_v.txt
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VECTOR DrivesTwo
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INPUT A 0 0
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INPUT A 3 1
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INPUT A 4 0
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7
circuit/circuit8.txt
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7
circuit/circuit8.txt
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CIRCUIT WhiteBoard
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INPUT A 1
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INPUT B 2
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OUTPUT C 3
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AND 2ns 1 2 4
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OR 3ns 2 4 3
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5
circuit/circuit8_v.txt
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5
circuit/circuit8_v.txt
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@ -0,0 +1,5 @@
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VECTOR WhiteBoard
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INPUT A 0 1
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INPUT B 0 0
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INPUT A 3 0
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7
circuit/ff.txt
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7
circuit/ff.txt
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CIRCUIT flipflop1
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INPUT R 1
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INPUT S 2
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OUTPUT O 3
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NOR 2ns 2 3 4
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NOR 2ns 1 4 3
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12
circuit/ff_v.txt
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12
circuit/ff_v.txt
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VECTOR flipflop1
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INPUT R 0 1
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INPUT S 0 1
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INPUT R 1 0
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INPUT S 1 0
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INPUT S 2 1
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INPUT S 3 0
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INPUT S 5 1
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INPUT S 6 0
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INPUT R 9 1
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INPUT R 10 0
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BIN
circuit/text circuit sim.exe
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BIN
circuit/text circuit sim.exe
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Binary file not shown.
@ -22,13 +22,9 @@ bool Simulation::parseCircuit(string fileName)
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in >> tmpString;
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in >> tmp1;
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if (tmpType == "INPUT") {
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tmpWire = new Wire(tmp1, true, tmpString);
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wires.push_back(tmpWire);
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}
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else if (tmpType == "OUTPUT") {
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tmpWire = new Wire(tmp1, false, tmpString);
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wires.push_back(tmpWire);
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if (tmpType == "INPUT" || tmpType == "OUTPUT") {
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tmpWire = findWire(tmp1);
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tmpWire->convertToIO(tmpString);
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}
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else if (tmpType == "NOT") {
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in >> tmp2;
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@ -126,7 +122,11 @@ Wire * Simulation::findWire(int n)
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for (auto i = wires.begin(); i != wires.end(); ++i) {
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if (n == (**i).getNumber()) return *i;
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}
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return nullptr;
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// if wire does not exist, create it, instantiating as an intermediary wire
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Wire * tmpWire = new Wire(n, false);
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wires.push_back(tmpWire);
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return tmpWire;
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}
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int Simulation::getDelay(string d)
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string fileName;
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Simulation e;
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cout << "Please enter filename: ";
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getline(cin, fileName);
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e.parseCircuit(fileName);
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