add comments to most files

This commit is contained in:
Joel Beckmeyer 2017-04-26 11:20:20 -04:00
parent ed164155f8
commit 8a4a0b8423
11 changed files with 29 additions and 1 deletions

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@ -8,6 +8,8 @@ AndGate::AndGate(int d, Wire* wire1, Wire* wire2, Wire* wire3) {
in2 = wire2;
out = wire3;
}
// generate an event based on changes in the Gate's inputs
Event AndGate::evaluate(int evTime) {
if (in1->getValue(evTime) == 0 || in2->getValue(evTime) == 0) {
return Event(0, evTime + delay, out);

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@ -1,5 +1,6 @@
#include "Event.h"
// static integer to keep track of current number of events
int Event::numOfEvents = 0;
Event::Event(int value, int setTime, Wire * output){
@ -29,6 +30,7 @@ void Event::setNum(int num)
evNum = num;
}
// < operator so that Event can be used in a priority_queue
bool operator<(const Event &e1, const Event &e2) {
if(e1.evTime == e2.evTime) {
return e1.evNum > e2.evNum;

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@ -5,6 +5,8 @@
class Wire;
// this class provides a base class for all other Gate classes (provided in
// other files)
class Gate {
public:
virtual Event evaluate(int) = 0;

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@ -9,6 +9,7 @@ NandGate::NandGate(int d, Wire * wire1, Wire * wire2, Wire * wire3)
out = wire3;
}
// generate an event based on changes in the Gate's inputs
Event NandGate::evaluate(int evTime)
{
if (in1->getValue(evTime) == 0 || in2->getValue(evTime) == 0) {

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@ -9,6 +9,7 @@ NorGate::NorGate(int d, Wire* wire1, Wire* wire2, Wire* wire3) {
out = wire3;
}
// generate an event based on changes in the Gate's inputs
Event NorGate::evaluate(int evTime) {
if (in1->getValue(evTime) == 1 || in2->getValue(evTime) == 1) {
return Event(0, evTime + delay, out);

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@ -8,6 +8,7 @@ NotGate::NotGate(int d, Wire* wire1, Wire* wire2) {
out = wire2;
}
// generate an event based on changes in the Gate's inputs
Event NotGate::evaluate(int evTime) {
if (in1->getValue(evTime) == 1) {
return Event(0, evTime + delay, out);

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@ -9,6 +9,7 @@ OrGate::OrGate(int d, Wire* wire1, Wire* wire2, Wire* wire3) {
out = wire3;
}
// generate an event based on changes in the Gate's inputs
Event OrGate::evaluate(int evTime) {
if (in1->getValue(evTime) == 1 || in2->getValue(evTime) == 1) {
return Event(1, evTime + delay, out);

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@ -3,6 +3,7 @@
#include <iomanip>
#include <sstream>
// parse the Circuit file and create in memory data structure
bool Simulation::parseCircuit(string fileName)
{
ifstream in;
@ -25,10 +26,12 @@ bool Simulation::parseCircuit(string fileName)
if (!(in >> tmpString)) break;
if (!(in >> tmp1)) break;
// create an in-memory wire
if (tmpType == "INPUT" || tmpType == "OUTPUT") {
tmpWire = findWire(tmp1);
tmpWire->convertToIO(tmpString);
}
// rest of blocks deal with gates and have nearly identical structures
else if (tmpType == "NOT") {
in >> tmp2;
tmpGate = new NotGate(getDelay(tmpString), findWire(tmp1),
@ -103,11 +106,12 @@ bool Simulation::parseCircuit(string fileName)
return true;
}
// parse the Vector file and add provided events to the priority_queue
bool Simulation::parseVector(string fileName) {
ifstream in;
in.open(fileName + "_v.txt");
if (in.fail()) {
cerr << endl << fileName << "_v.txt could not be opened :(";
cerr << endl << fileName << "_v.txt could not be opened :(\n";
return false;
}
@ -118,12 +122,14 @@ bool Simulation::parseVector(string fileName) {
// get rid of first line
getline(in, tmpString);
// pull in all data from Vector file
while(true) {
if (!(in >> tmpString)) break;
if (!(in >> tmpString)) break;
if (!(in >> timeInt)) break;
if (!(in >> valInt)) break;
// find wire with provided name
for(auto i = wires.begin(); i != wires.end(); ++i) {
if((**i).getName() == tmpString) {
tmpWire = *i;
@ -139,6 +145,7 @@ bool Simulation::parseVector(string fileName) {
}
}
// simulate the circuit using the provided in-memory circuit and queue of events
void Simulation::simulate(int simTime) {
// loop through event queue
while(!e.empty()) {
@ -171,6 +178,7 @@ void Simulation::simulate(int simTime) {
}
}
// print each wire's trace
void Simulation::print(int simTime)
{
int lastTime = 0;
@ -200,6 +208,8 @@ void Simulation::print(int simTime)
cout << t << endl;
}
// iterate through wires vector and find wire with provided number; if wire does
// not exist, create a new one
Wire * Simulation::findWire(int n)
{
for (auto i = wires.begin(); i != wires.end(); ++i) {

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@ -9,6 +9,7 @@ XnorGate::XnorGate(int d, Wire* wire1, Wire* wire2, Wire* wire3) {
out = wire3;
}
// generate an event based on changes in the Gate's inputs
Event XnorGate::evaluate(int evTime) {
if (in1->getValue(evTime) != -1 && in2->getValue(evTime) != -1) {
if (in1->getValue(evTime) == in2->getValue(evTime)) {

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@ -9,6 +9,7 @@ XorGate::XorGate(int d, Wire* wire1, Wire* wire2, Wire* wire3) {
out = wire3;
}
// generate an event based on changes in the Gate's inputs
Event XorGate::evaluate(int evTime) {
if (in1->getValue(evTime) != -1 && in2->getValue(evTime) != -1) {
if (in1->getValue(evTime) != in2->getValue(evTime)) {

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@ -1,3 +1,9 @@
// Name: radec.cpp
// Author: Joel Beckmeyer, Daniel Parker
// Date: 2017-04-26
// Purpose: to use the library we have developed in order to simulate a boolean
// logic circuit
#include "Simulation.h"
using namespace std;