make parseCircuit() push gates onto input wire gates vector
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@ -32,49 +32,71 @@ bool Simulation::parseCircuit(string fileName)
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in >> tmp2;
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tmpGate = new NotGate(getDelay(tmpString), findWire(tmp1),
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findWire(tmp2));
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// push gate onto Simulation gates vector
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gates.push_back(tmpGate);
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// also push gate onto input wire's gate vector
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findWire(tmp1)->addGate(tmpGate);
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}
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else if (tmpType == "AND") {
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in >> tmp2;
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in >> tmp3;
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tmpGate = new AndGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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findWire(tmp1)->addGate(tmpGate);
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findWire(tmp2)->addGate(tmpGate);
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}
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else if (tmpType == "NAND") {
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in >> tmp2;
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in >> tmp3;
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tmpGate = new NandGate(getDelay(tmpString), findWire(tmp1),
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findWire(tmp2), findWire(tmp3));
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gates.push_back(tmpGate);
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findWire(tmp1)->addGate(tmpGate);
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findWire(tmp2)->addGate(tmpGate);
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}
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else if (tmpType == "OR") {
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in >> tmp2;
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in >> tmp3;
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tmpGate = new OrGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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findWire(tmp1)->addGate(tmpGate);
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findWire(tmp2)->addGate(tmpGate);
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}
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else if (tmpType == "XOR") {
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in >> tmp2;
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in >> tmp3;
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tmpGate = new XorGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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findWire(tmp1)->addGate(tmpGate);
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findWire(tmp2)->addGate(tmpGate);
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}
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else if (tmpType == "NOR") {
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in >> tmp2;
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in >> tmp3;
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tmpGate = new NorGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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findWire(tmp1)->addGate(tmpGate);
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findWire(tmp2)->addGate(tmpGate);
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}
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else if (tmpType == "XNOR") {
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in >> tmp2;
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in >> tmp3;
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tmpGate = new XnorGate(getDelay(tmpString), findWire(tmp1), findWire(tmp2),
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findWire(tmp3));
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gates.push_back(tmpGate);
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findWire(tmp1)->addGate(tmpGate);
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findWire(tmp2)->addGate(tmpGate);
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}
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}
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return true;
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