A simple, terminal-based boolean logic simulator
Go to file
2017-04-23 19:53:37 -04:00
Radec Fix the gate evaluate definition to return event 2017-04-23 19:29:29 -04:00
src Add a setOut to the gate parent class 2017-04-23 19:53:37 -04:00
.gitattributes Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
.gitignore Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
readme.md Added something to the TODO. 2017-04-20 13:02:48 -04:00

RADEC

TODO

  • implement vector file parsing
  • define all classes more completely
  • Add constructors for the gate classes which are used in the simulation class to make them.