A simple, terminal-based boolean logic simulator

logic logic-circuit logic-gates terminal-based

Go to file

daniel 40d0957420 Merge branch 'master' of https://daniel12997@gitlab.com/AluminumTank/radec.git		2017-04-25 13:50:17 -04:00
Radec	just some housekeeping	2017-04-25 13:50:13 -04:00
circuit	just some housekeeping	2017-04-25 13:50:13 -04:00
src	fix another feedback loop issue	2017-04-25 12:24:53 -04:00
.gitattributes	Add the basic class defineition for Wire and Gate.	2017-04-04 13:37:46 -04:00
.gitignore	Add the basic class defineition for Wire and Gate.	2017-04-04 13:37:46 -04:00
readme.md	update readme	2017-04-24 22:41:01 -04:00

readme.md

RADEC

TODO

debug: circuit parsing
debug: vector parsing
debug: simulation
debug: printing