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A simple, terminal-based boolean logic simulator
100 Commits 1 Branch 0 Tags 429 KiB
C++ 99.4%
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93612d7e1d
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Joel Beckmeyer 93612d7e1d implement new method to make file parsing more robust
2017-04-24 22:55:37 -04:00
circuit add the amazing test cases 2017-04-23 20:57:44 -04:00
Radec stuff 2017-04-24 22:14:00 -04:00
src implement new method to make file parsing more robust 2017-04-24 22:55:37 -04:00
.gitattributes Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
.gitignore Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
readme.md update readme 2017-04-24 22:41:01 -04:00

readme.md

RADEC

TODO

  • debug: circuit parsing
  • debug: vector parsing
  • debug: simulation
  • debug: printing