TnSb/radec
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
103 Commits 1 Branch 0 Tags
93a176884dc06a8752dd13726a694a3cc75a67dc
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Joel Beckmeyer 93a176884d fix naming error
2017-04-25 09:08:16 -04:00
circuit
add the amazing test cases
2017-04-23 20:57:44 -04:00
Radec
stuff
2017-04-24 22:14:00 -04:00
src
fix naming error
2017-04-25 09:08:16 -04:00
.gitattributes
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
.gitignore
Add the basic class defineition for Wire and Gate.
2017-04-04 13:37:46 -04:00
readme.md
update readme
2017-04-24 22:41:01 -04:00

readme.md

RADEC

TODO

  • debug: circuit parsing
  • debug: vector parsing
  • debug: simulation
  • debug: printing
Description
A simple, terminal-based boolean logic simulator
logiclogic-circuitlogic-gatesterminal-based
Readme 429 KiB
Languages
C++ 99.4%
Batchfile 0.6%