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A simple, terminal-based boolean logic simulator
13 Commits 1 Branch 0 Tags 429 KiB
C++ 99.4%
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Joel Beckmeyer 46fc86d36a update readme
2017-04-09 21:44:46 -04:00
Radec Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
src implement circuit file parsing and add specs for rest of gates 2017-04-09 21:42:07 -04:00
.gitattributes Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
.gitignore Add the basic class defineition for Wire and Gate. 2017-04-04 13:37:46 -04:00
readme.md update readme 2017-04-09 21:44:46 -04:00

readme.md

RADEC

TODO

  • implement findWire() function
  • implement vector file parsing
  • develop pQueue class
  • define all classes more completely