2017-04-24 22:39:40 -04:00
2017-04-23 20:57:44 -04:00
2017-04-24 22:14:00 -04:00
2017-04-24 22:39:40 -04:00
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RADEC

TODO

  • implement printing
  • debug: circuit parsing
  • debug: vector parsing
  • debug: simulation
  • debug: printing
Description
A simple, terminal-based boolean logic simulator
Readme 429 KiB
Languages
C++ 99.4%
Batchfile 0.6%